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CMOS ST-BUSTM Family MT89L80 Digital Switch
Data Sheet Features
* * * * * * * * * * 3.3 volt supply 5 V tolerant inputs and TTL compatible outputs. 256 x 256 channel non-blocking switch Accepts serial streams at 2.048 Mb/s Per-channel three-state control Patented per channel message mode Non-multiplexed microprocessor interface Zarlink ST-BUS compatible Low power consumption: typical 15 mW Pin compatible with the MT8980DP Ordering Information
MT89L80ANR 48 Pin SSOP MT89L80APR 44 Pin PLCC MT89L80AP 44 Pin PLCC MT89L80AN 48 Pin SSOP MT89L80APR1 44 Pin PLCC* MT89L80ANR1 48 Pin SSOP* MT89L80AN1 48 Pin SSOP* MT89L80AP1 44 Pin PLCC* *Pb Free Matte Tin Tape & Reel Tape & Reel Tubes Tubes Tape & Reel Tubes Tubes Tubes
Sept. 2006
-40C to +85C
Description
This VLSI CMOS device is designed for switching PCM-encoded voice or data, under microprocessor control, in a modern digital exchange, PBX or Central Office. It provides simultaneous connections for up to 256 64 kbit/s channels. Each of the eight serial inputs and outputs consist of 32 64 kbit/s channels multiplexed to form a 2048 kbit/s ST-BUS stream. In addition, the MT89L80 provides microprocessor read and write access to individual ST-BUS channels.
Applications
* * * Key telephone systems PBX systems Small and medium voice switching systems
C4i
F0i RESET VDD VSS
**
ODE
STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 Serial to Parallel Converter Data Memory
Frame Counter
Output MUX Parallel to Serial Converter
STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7
Control Register
Connection Memory
Control Interface
DS CS R/W A5/ A0
DTA D7/ D0
CSTo ** for 48-pin SSOP only
Figure 1 - Functional Block Diagram
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Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
MT89L80
Data Sheet
NC STi2 STi1 STi0 DTA CSTo ODE STo0 STo1 STo2 NC
STi3 STi4 STi5 STi6 STi7 VDD F0i C4i A0 A1 A2
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
STo3 STo4 STo5 STo6 STo7 VSS D0 D1 D2 D3 D4
VSS DTA STi0 STi1 STi2 NC STi3 STi4 STi5 STi6 STi7 VDD RESET F0i C4i A0 A1 A2 NC A3 A4 A5 DS R/W
44 PIN PLCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
CSTo ODE STo0 STo1 STo2 NC STo3 STo4 STo5 STo6 STo7 VSS VDD D0 D1 D2 D3 D4 NC D5 D6 D7 CS VSS
NC A3 A4 A5 DS R/W CS D7 D6 D5 NC
18 19 20 21 22 23 24 25 26 27 28
6 5 4 3 2 1 44 43 42 41 40
48 PIN SSOP (JEDEC MO-118, 300mil Wide)
Figure 2 - Pin Connections Pin Description Pin # 44 48 PLCC SSOP 2 2 Name DTA Description Data Acknowledgment (5 V Tolerant Three-state Output). This active low output indicates that a data bus transfer is complete. A pull-up resistor is required at this output.
3-5 7-11 12
3-5 7-11 12,36 13
STi0-2 ST-BUS Inputs 0 to 2 (5 V-tolerant Inputs). Serial data input streams. These streams have data rates of 2.048 Mbit/s with 32 channels. STi3-7 ST-BUS Inputs 3 to 7 (5 V-tolerant Inputs). Serial data input streams. These streams may have data rates of 2.048 Mbit/s with 32channels. VDD +3.3 Volt Power Supply. RESET Device Reset (5 V-tolerant input). This pin is only available for the 48-pin SSOP package.This active low input puts the device in its reset state. It clears the internal counters and registers. All ST-BUS outputs are set to the high impedance state. In normal operation. The RESET pin must be held low for a minimum of 100nsec to reset the device. Internal pull-up. F0i Frame Pulse (5 V-tolerant Input). This is the input for the frame synchronization pulse for the 2048 kbit/s ST-BUS streams. A low on this input causes the internal counter to reset on the next negative transition of C4i.
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Pin Description (continued) Pin # 44 48 PLCC SSOP 14 15-17 19-21 22 23 24 25-27 29-33 34 35-39 41-43 44 15 16-18 20-22 23 24 26 27-29 31-35 1, 25,37 38-42 44-46 47 Name C4i A0-2 A3-5 DS R/W CS D7-D5 D4-D0 VSS Description
Data Sheet
4.096 MHz Clock (5 V-tolerant Input). ST-BUS bit cell boundaries lie on the alternate falling edges of this clock. Address 0-2 / Input Streams 8-10 (5 V-tolerant Input). These are the inputs for the address lines on the microprocessor interface. Address 3-5 / Input Streams 11-13 (5 V-tolerant Input). These are the inputs for the address lines on the microprocessor interface. Data Strobe (5 V-tolerant Input). This is the input for the active high data strobe on the microprocessor interface. Read/Write (5 V-tolerant Input). This is the input for the read/write signal on the microprocessor interface - high for read, low for write. Chip Select (5 V-tolerant Input). This is the input for the active low chip select on the microprocessor interface Data Bus (5 V-tolerant I/O): These are the bidirectional data pins on the microprocessor interface. Data Bus (5 V-tolerant I/O): These are the bidirectional data pins on the microprocessor interface. Ground.
STo7-3 ST-BUS Outputs 7 to 3 (5 V-Tolerant Three-state Outputs). These are the pins for the eight 2048 kbit/s ST-BUS output streams. STo2-0 ST-BUS Outputs 2to 0 (5 V-Tolerant Three-state Outputs). These are the pins for the eight 2048kbit/s ST-BUS output streams. ODE Output Drive Enable (5 V-tolerant Input). If this input is held high, the STo0-STo7 output drivers function normally. If this input is low, the STo0-STo7 output drivers go into their high impedance state. NB: Even when ODE is high, channels on the STo0-STo7 outputs can go high impedance under software control. Control ST-BUS Output (5 V-Tolerant Output). Each frame of 256 bits on this ST-BUS output contains the values of bit 1 in the 256 locations of the Connection Memory High. No Connection.
1
48
CSTo NC
6, 18, 6, 19, 28, 40 30, 43
Functional Description
In recent years, there has been a trend in telephony towards digital switching, particularly in association with software control. Simultaneously, there has been a trend in system architectures towards distributed processing or multi-processor systems. In accordance with these trends, Zarlink has devised the ST-BUS (Serial Telecom Bus). This bus architecture can be used both in software-controlled digital voice and data switching, and for interprocessor communications. The uses in switching and in interprocessor communications are completely integrated to allow for a simple general purpose architecture appropriate for the systems of the future.
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Zarlink Semiconductor Inc.
MT89L80
Data Sheet
The serial streams of the ST-BUS operate continuously at 2048 kbit/s and are arranged in 125 s wide frames which contain 32 8-bit channels. Zarlink manufactures a number of devices which interface to the ST-BUS; a key device being the MT89L80 chip. The MT89L80 can switch data from channels on ST-BUS inputs to channels on ST-BUS outputs, and simultaneously allows its controlling microprocessor to read channels on ST-BUS inputs or write to channels on STBUS outputs (Message Mode). To the microprocessor, the MT89L80 looks like a memory peripheral. The microprocessor can write to the MT89L80 to establish switched connections between input ST-BUS channels and output ST-BUS channels, or to transmit messages on output ST-BUS channels. By reading from the MT89L80, the microprocessor can receive messages from ST-BUS input channels or check which switched connections have already been established. By integrating both switching and interprocessor communications, the MT89L80 allows systems to use distributed processing and to switch voice or data in an ST-BUS architecture. Hardware Description Serial data at 2048 kbit/s is received at the eight ST-BUS inputs (STi0 to STi7), and serial data is transmitted at the eight ST-BUS outputs (STo0 to STo7). Each serial input accepts 32 channels of digital data, each channel containing an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec (e.g., Zarlink's MT8964). This serial input word is converted into parallel data and stored in the 256 X 8 Data Memory. Locations in the Data Memory are associated with particular channels on particular ST-BUS input streams. These locations can be read by the microprocessor which controls the chip. Locations in the Connection Memory, which is split into high and low parts, are associated with particular ST-BUS output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be switched from an ST-BUS input or it can originate from the microprocessor. If the data is switched from an input, then the contents of the Connection Memory Low location associated with the output channel is used to address the Data Memory. This Data Memory address corresponds to the channel on the input ST-BUS stream on which the data for switching arrived. If the data for the output channel originates from the microprocessor (Message Mode), then the contents of the Connection Memory Low location associated with the output channel are output directly, and this data is output repetitively on the channel once every frame until the microprocessor intervenes. The Connection Memory data is received, via the Control Interface, at D7 to D0. The Control Interface also receives address information at A5 to A0 and handles the microprocessor control signals CS, DTA, R/W and DS. There are two parts to any address in the Data Memory or Connection Memory. The higher order bits come from the Control Register, which may be written to or read from via the Control Interface. The lower order bits come from the address lines directly. The Control Register also allows the chip to broadcast messages on all ST-BUS outputs (i.e., to put every channel into Message Mode), or to split the memory so that reads are from the Data Memory and writes are to the Connection Memory Low. The Connection Memory High determines whether individual output channels are in Message Mode, and allows individual output channels to go into a high-impedance state, which enables arrays of MT89L80s to be constructed. It also controls the CSTo pin. All ST-BUS timing is derived from the two signals C4i and F0i.
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Zarlink Semiconductor Inc.
MT89L80
A5 0 1 1 * * * 1 A4 0 0 0 * * * 1 A3 0 0 0 * * * 1 A2 0 0 0 * * * 1 A1 0 0 0 * * * 1 A0 0 0 1 * * * 1 Hex Address 00 - 1F 20 21 * * * 3F Location Control Register * Channel 0 Channel 1 * * * Channel 31
Data Sheet
* Writing to the Control Register is the only fast transaction. Memory and stream are specified by the contents of the Control Register. Figure 3 - Address Memory Map Software Control The address lines on the Control Interface give access to the Control Register directly or, depending on the contents of the Control Register, to the High or Low sections of the Connection Memory or to the Data Memory. If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Fig. 3). If A5 is high, then the address lines A4-A0 select the memory location corresponding to channel 0-31 for the memory and stream selected in the Control Register. The data in the Control Register consists of mode control bits, memory select bits, and stream address bits (see Fig. 4). The memory select bits allow the Connection Memory High or Low or the Data Memory to be chosen, and the stream address bits define one of the ST-BUS input or output streams. Bit 7 of the Control Register allows split memory operation - reads are from the Data Memory and writes are to the Connection Memory Low. The other mode control bit, bit 6, puts every output channel on every output stream into active Message Mode; i.e., the contents of the Connection Memory Low are output on the ST-BUS output streams once every frame unless the ODE pin is low. In this mode the chip behaves as if bits 2 and 0 of every Connection Memory High location were 1, regardless of the actual values.
(unused) Mode Control Bits Memory Select Bits Stream Address Bits
7
6
5
4
3
2
1
0
Bit 7
Name
Description
Split Memory When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory Low, except when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for subsequent operations. In either case, the Stream Address Bits select the subsection of the memory which is made available.
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Zarlink Semiconductor Inc.
MT89L80
(unused) Mode Control Bits Memory Select Bits Stream Address Bits
Data Sheet
7
6
5
4
3
2
1
0
Bit 6
Name Message Mode (unused) Memory Select Bits
Description When 1, the contents of the Connection Memory Low are output on the Serial Output streams except when the ODE pin is low. When 0, the Connection Memory bits for each channel determine what is output. 0-0 - Not to be used 0-1 - Data Memory (read only from the microprocessor port) 1-0 - Connection Memory Low 1-1 - Connection Memory High
5 4-3
2-0
Stream The number expressed in binary notation on these bits refers to the input or output ST-BUS Address Bits stream which corresponds to the subsection of memory made accessible for subsequent operations. Figure 4 - Control Register Bits
No Corresponding Memory - These bits give 0s if read.
Per Channel Control Bits
7
6
5
4
3
2
1
0
Bit 2
Name Message Channel
Description When 1, the contents of the corresponding location in Connection Memory Low are output on the location's channel and stream. When 0, the contents of the corresponding location in Connection Memory Low act as an address for the Data Memory and so determine the source of the connection to the location's channel and stream. This bit is output on the CSTo pin one channel early. The CSTo bit for stream 0 is output first. If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the output driver for the location's channel and stream. This allows individual channels on individual streams to be made high-impedance, allowing switching matrices to be constructed. A 1 enables the driver and a 0 disables it. Figure 5 - Connection Memory High Bits
1 0
CSTo Bit Output Enable
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Zarlink Semiconductor Inc.
MT89L80
Data Sheet
Stream Address Bits
Channel Address Bits
7
6
5
4
3
2
1
0
Bit 7-5*
Name Stream Address Bits* Channel Address Bits*
Description The number expressed in binary notation on these 3 bits is the number of the ST-BUS stream for the source of the connection. Bit 7 is the most significant bit. e.g., if bit 7 is 1, bit 6 is 0 and bit 5 is 0, then the source of the connection is a channel on STi4. The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the connection (The ST-BUS stream where the channel lies is defined by bits 7, 6 and 5.). Bit 4 is the most significant bit. e.g., if bit 4 is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.
4-0*
*If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location. Figure 6 - Connection Memory Low Bits If bit 6 of the Control Register is 0, then bits 2 and 0 of each Connection Memory High location function normally (see Fig. 5). If bit 2 is 1, the associated ST-BUS output channel is in Message Mode; i.e., the byte in the corresponding Connection Memory Low location is transmitted on the stream at that channel. Otherwise, one of the bytes received on the serial inputs is transmitted and the contents of the Connection Memory Low define the STBUS input stream and channel where the byte is to be found (see Fig. 6). If the ODE pin is low, then all serial outputs are high-impedance. If it is high and bit 6 in the Control Register is 1, then all outputs are active. If the ODE pin is high and bit 6 in the Control Register is 0, then the bit 0 in the Connection Memory High location enables the output drivers for the corresponding individual ST-BUS output stream and channel. Bit 0=1 enables the driver and bit 0=0 disables it (see Fig. 5). Bit 1 of each Connection Memory High location (see Fig. 5) is output on the CSTo pin once every frame. To allow for delay in any external control circuitry the bit is output one channel before the corresponding channel on the ST-BUS streams, and the bit for stream 0 is output first in the channel; e.g., bit 1's for channel 9 of streams 0-7 are output synchronously with ST-BUS channel 8 bits 7-0.
Applications
Use in a Simple Digital Switching System Figs. 7 and 8 show how MT89L80s can be used with MT8964s to form a simple digital switching system. Fig. 7 shows the interface between the MT89L80s and the filter/codecs. Fig. 8 shows the position of these components in an example architecture. The MT8964 filter/codec in Fig. 7 receives and transmits digitized voice signals on the ST-BUS input DR, and STBUS output DX, respectively. These signals are routed to the ST-BUS inputs and outputs on the top MT89L80, which is used as a digital speech switch. The MT8964 is controlled by the ST-BUS input DC originating from the bottom MT89L80, which generates the appropriate signals from an output channel in Message Mode. This architecture optimizes the messaging capability
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Zarlink Semiconductor Inc.
MT89L80
Data Sheet
of the line circuit by building signalling logic, e.g., for on-off hook detection, which communicates on an ST-BUS output. This signalling ST-BUS output is monitored by a microprocessor (not shown) through an ST-BUS input on the bottom MT89L80. Fig. 8 shows how a simple digital switching system may be designed using the ST-BUS architecture. This is a private telephone network with 256 extensions which uses a single MT89L80 as a speech switch and a second MT89L80 for communication with the line interface circuits.
STo0 STi0 89L80 used as speech switch MT89L80 DX DR DC STo0 STi0 89L80 used in message mode for control and signalling
MT8964 Filter/Codec
Signalling Logic
Line Driver and 2- to 4Wire Converter
Line Interface Circuit with 8964 Filter/Codec MT89L80
Figure 7 - Example of Typical Interface between 89L80s and 8964s for Simple Digital Switching System
Line Interface Circuit with Codec (e.g. 8964) 8 Speech Switch 89L80
STi0-7
Line 1
8
STo0-7
Controlling MicroProcessor
STo0-7
8
STi0-7
* * * Repeated for Lines 2 to 255
* * * Repeated for Lines 2 to 255
8 Control & Signalling 89L80
Line Interface Circuit with Codec (e.g.8964)
Line 256
Figure 8 - Example Architecture of a Simple Digital Switching System
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Zarlink Semiconductor Inc.
MT89L80
Absolute Maximum Ratings* Parameter 1 2 3 4 5 Supply Voltage Voltage on any I/O pin (except supply pins) Current at Digital Outputs Storage Temperature Package Power Dissipation VO IO TS PD -55 Symbol Min. -0.3 VSS-0.3 Max. 5.0
Data Sheet
Units V V mA C W
.
VDD+0.3 20 +125 1
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (Vss) unless otherwise stated. Characteristics 1 2 3 4 5 Operating Temperature Positive Supply Input High Voltage Input High Voltage on 5 V Tolerant Inputs Input Low Voltage Sym. TOP VDD VIH VIH VIL VSS Min. -40 3.0 0.7VDD Typ. Max. +85 3.6 VDD 5.5 0.3VDD Units C V V V V Test Conditions
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 10 11 I N P U T S O U T P U T S Supply Current Input High Voltage Input Low Voltage Input Leakage Input Pin Capacitance Output High Voltage Output High Current Output Low Voltage Output Low Current High Impedance Leakage Output Pin Capacitance Sym. IDD VIH VIL IIL CI VOH IOH VOL IOL IOZ CO 5 5 10 0.8VDD 10 0.4 0.7VDD 0.3VDD 5 10 Min. Typ. 4 Max. 7 Units mA V V A pF V mA V mA A pF IOH = 10 mA Sourcing. VOH=2.4V IOL = 5 mA Sinking. VOL = 0.4V VO between VSS and VDD VI between VSS and VDD Test Conditions Outputs unloaded
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics _Timing Parameter Measurement Voltage Levels Characteristics 1 2 3 CMOS Threshold Voltage CMOS Rise/Fall Threshold Voltage high CMOS Rise/Fall Threshold Voltage low Sym VTT VHM VLM Level 0.5VDD 0.7VDD 0.3VDD Units V V V Test Conditions
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AC Electrical Characteristics - Clock Timing (Figures 9 and 10) Characteristics 1 2 3 4 5 6 7 I N P U T S Clock Period* Clock Width High Clock Width Low Clock Transition Time Frame Pulse Setup Time Frame Pulse Hold Time Frame Pulse Width Sym. tCLK tCH tCL tCTT tFPS tFPH tFPW 10 10 244 Min. 220 85 85 Typ. 244 122 122 Max. 300 150 150 10 190 190 Units ns ns ns ns ns ns ns
Data Sheet
Test Conditions
Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state. NB: Frame Pulse is repeated every 512 cycles of C4i.
C4i
F0i
BIT CELLS
Channel 31 Bit o
Channel 0 Bit 7
Figure 9 - Frame Alignment
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Zarlink Semiconductor Inc.
MT89L80
Data Sheet
tCLK tCL VHM VLM tCHL tFPH F0i VHM VLM tFPW tFPS tCTT tFPH tFPS tCTT tCH
C4i
Figure 10 - Clock Timing AC Electrical Characteristics - Serial Streams (Figures 11, 12 and 13) Characteristics 1 2 3 4 5 6 7 O U T P U T S I N STo0/7 Delay - Active to High Z STo0/7 Delay - High Z to Active STo0/7 Delay - Active to Active Output Driver Enable Delay External Control Delay Serial Input Setup Time Serial Input Hold Time Sym. tSAZ tSZA tSAA tOED tXCD tSIS tSIH 20 20 Min. 5 5 5 Typ. Max. 55 55 55 50 55 Units ns ns ns ns ns ns ns Test Conditions RL=1 K*, CL=150 pF CL=150 pF CL=150 pF RL=1 K*, CL=150 pF CL=150 pF
Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
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Zarlink Semiconductor Inc.
MT89L80
Data Sheet
Bit Cell Boundary VHM C4i VLM
V STo0 HM to V STo7 LM tSAZ STo0 VHM to STo7 VLM
*
*
tSZA
V STo0 HM to V STo7 LM tSAA
VHM CSTo VLM tXCD
Figure 11 - Serial Outputs and External Control
ODE
VHM VLM
STo0 VHM to STo7 VLM
*
tOED tOED
*
Figure 12 - Output Driver Enable
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Zarlink Semiconductor Inc.
MT89L80
Data Sheet
Bit Cell Boundaries VHM C4i VLM tSIH STi0 VHM to STi7 VLM tSIS
Figure 13 - Serial Inputs AC Electrical Characteristics - Processor Bus (Figures 14) Characteristics 1 2 3 4 Chip Select Setup Time Read/Write Setup Time Address Setup Time Acknowledgment Delay Control Register Read Control Register Write Connection Memory Read Connection Memory Write Data Memory Read 5 6 7 8 9 10 11 12 13 Fast Write Data Setup Time Slow Write Data Delay Read Data Setup Time Data Hold Time Read Write Read Data To High Impedance Chip Select Hold Time Read/Write Hold Time Address Hold Time Acknowledgment Hold Time tAKD tAKD tAKD tAKD tAKD tFWS tSWD tRDS tDHT tDHT tRDZ tCSH tRWH tADH tAKH 0 10 5 15 0 0 8 50 80 10 50 90 90 0 122 52 25 62 30 560 120 65 120 53 1220 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns RL=1 K, CL=150 pF RL=1 K, CL=150 pF CL= 150 pF RL=1 K, CL=150 pF CL=150 pF CL=150 pF CL=150 pF CL=150 pF CL=150 pF Sym tCSS tRWS tADS Min 0 5 5 Typ Max Units ns ns ns Test Conditions
Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. * High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
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Zarlink Semiconductor Inc.
MT89L80
Data Sheet
DS
VHM VLM VHM VLM tCSS tCSH VHM VLM tRWS tRWH VHM VLM tADS tAKD tADH tAKH
CS
R/W
A5 to A0
DTA
VHM VLM VHM VLM
*
tRDS tDHT
*
D7 to D0
*
tSWD tFWS tRDZ
*
Figure 14 - Processor Bus
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c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes
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Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved.
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